The invention relates to a method for the manufacture of cross-couplings between n-channel and p-channel CMOS field effect transistors of static write-read memories (SRAMs) wherein, in accordance with known method steps of CMOS technology (manufacture of complementary CMOS transistors), buried contacts to the diffused n.sup.+ and p.sup.+ regions of the transistors in the substrate are produced. The gate level is formed of doped polysilicon, and metal silicide is employed as an additional wiring level for the cross-coupling between n-channel and p-channel transistors. The invention also relates to the use of this method for the manufacture of a static 6-transistor memory cell arrangement.
The functioning of a static 6-transistor memory cell as well as its structure can be derived, for example, from the book by Lucke, Mize, Carr, "Semiconductor Memory Design and Application", McGraw Hill, Kogakusha Ltd., FIG. 5.3, page 118, incorporated herein by reference. A disadvantage of this cell in comparison to the dynamic 1-transistor cell is the great space requirement, also due to the required cross-couplings.
The cross-couplings between n-channel and p-channel transistors is a problem, particularly in the CMOS-SRAM cells. In known CMOS technologies with a gate of n.sup.+ doped polysilicon or of n.sup.+ doped double layers of polysilicon and metal silicide, buried contacts to n.sup.+ doped and p.sup.+ doped regions at the same time are not possible. The cross-connections must be produced via additional metal bridges. Additional metal grids for each cell are therefore required, these having a distinctly negative effect on the packing density.
A miniaturization of the static RAM cells is enabled by the use of additional wiring levels which, for example, are formed of polysilicon or aluminum. Two method steps of photolithography and of etching respectively arise for each wiring level. The realization of buried contacts to n.sup.+ and p.sup.+ regions allows the gate level to be used for the required cross-couplings. An auxiliary wiring level can thus be eliminated or, given a constant number of wiring levels, the packing density can be increased.
A method such as that initially cited is recited in a report by Kudoh et al in IEDM Technical Digest 1984, pages 67-70, incorporated herein by reference. It is based on the process of selective silicating, a method which is difficult to manage, and contains mask-intensive steps for local n.sup.+ or p.sup.+ doping of the polysilicon regions before the silicating.